The invention relates generally to semiconductor devices. More particularly, this invention relates to configurations and methods to manufacture a cascoded junction field effect transistor (JFET) device including a high voltage and a low voltage JFET to achieve wide operating voltage capability with tight pinch-off voltage (Vp) variations, especially for lower voltage devices.
The processes for manufacturing the conventional high voltage junction field effect transistor (JFET) device is limited by the highly sensitive performance variations caused by the thickness variations of the epitaxial layer functioning as the channel region. A conventional JFET device is formed either as a high voltage JFET device or a low voltage device, as shown in FIGS. 1A and 1B, respectively.
U.S. Pat. No. 4,675,713 discloses a method of using the source Schottky junction as the body contact for a semiconductor power device. U.S. Pat. No. 4,983,535 discloses a fabrication method to manufacture a DMOS device with a source implemented with a refractory metal Schottky barrier located on top of the body region. However, these devices still have the limitations of using metals of relatively high barrier height. The device performance cannot satisfy the modern applications that require further reduction on resistance and higher drive currents.
In the conventional high voltage JFET of FIG. 1A, the channel region, e.g., an N-channel region, is formed laterally under a P-type gate region between the source and the drain regions. The N-channel region is provided in an N-region and/or an N-type epitaxial (N-epi) layer (the N-epi layer may be grown on a P-type substrate). The N-channel is formed by the portions of the N-region and N-epi located between the P-gate region and the P-type substrate.
An effective thickness, t, of the N-channel varies according to the thickness variations of the epitaxial layer. The pinch-off voltage Vp of the JFET device thus varies with the thickness variations of the epitaxial layer, which can be large due to variabilities in manufacturing, effective doping of N-region and epitaxial layer, effective depth of P-gate region and auto-doping at N-epitaxial layer/P-type substrate interface during epitaxial growth. Because of channel thickness variations due to variations in the thickness of the N-epitaxial layer, the variations of the pinch off voltage Vp can be quite significant across each wafer, and from wafer to wafer and from lot to lot depending on variations in manufacturing conditions for each wafer and each lot.
Such Vp variations may be unacceptably large, especially when deep submicron technologies are implemented. Devices manufactured with deep submicron technologies usually have tight requirements for the maximum and typical operating voltages, i.e., there may not be a large margin between the maximum operating voltage and the typical operating voltages. For example, a 2 um device might have a 5V typical operating voltage and a 10V maximum voltage, whereas a 0.5 um device might have a 5V typical operating voltage and only a 6V maximum voltage. In the meantime, the pinch off voltage, Vp, of a JFET device must be lower than the absolute maximum voltage. But if the pinch off voltage Vp has large variations, the target pinch off voltage Vp must also be reduced accordingly to ensure that it does not exceed the maximum allowed voltage, resulting in a weaker JFET device. A JFET with a low Vp typically has a large channel resistance and cannot handle much current for its given size. In order to overcome the current-handling limitations due to lower Vp (e.g. caused by the epitaxial layer thickness variations), a JFET device needs to be implemented with greater size to provide greater channel area and better current handling capability. The size and production costs of such JFET devices are therefore increased.
On the other hand, an N-channel JFET with a shallow N-channel implant and shallow top gate implant to achieve a tight control over the Vp variation can be manufactured, like the conventional low voltage JFET shown in FIG. 1B. However, a JFET with shallow channel and gate region implant has a low operating voltage. Devices manufactured with such configurations can therefore be operated only with low operating voltages. For higher voltage operations, there are still limitations and difficulties for JFET devices manufactured with the conventional processes and configurations due to the thickness variations of the epitaxial layer and the sensitivities of the pinch off voltage (Vp) variations caused by these thickness variations.
In US Patent Application 2007/0012958, Hower et al. discloses a Junction Field Effect Transistor (JFET) that is fabricated with a well region functioning as a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET. The invention may be able to reduce the pinch off voltage but the teachings would not resolve the difficulties that high voltage applications with JFET devices are required to implement with greater size in order to overcome the limitations due to the uncertainties of the pinch off voltage.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new device configurations and manufacturing methods for forming the JFET power device such that the above discussed problems and limitations can be resolved.